1. Field of the Disclosure
The present invention relates to a serial interface and an apparatus and method for serial interfacing, and more particularly, to an apparatus including a serial interface and a method for serial interfacing in which data input/reception and reset functions are possible using a duty or duty cycle of an input signal.
2. Discussion of the Related Art
As mobile devices pursue size reduction, high integration, and low power consumption, the size of components used in mobile devices is being reduced, and power terminals and signal terminals are being simplified. Especially, as internal signal terminals in mobile devices such as cellular phones, PMPs, and MP3 players, instead of conventional buses, high speed Serial Interfaces are increasingly used due to their low power consumption, contribution to size reduction, high-speed capability and/or operations, and simple design.
The signal transmission method simplified as described above was typically embodied as I2C, USB, or One-Wire, presently. Especially, the One-Wire interface, having a powerful performance in making fast transmission/reception of signals among a plurality of chip components through one signal terminal, is widely used in cellular phones.
FIG. 1 illustrates a block diagram of an integrated circuit (IC) that includes a conventional single wire interface. The IC includes an input, an output, an enable/set or reset (EN/SET) input, and a core portion 10. The core portion 10 is intended to be generally representative of circuits that function to create an output signal (e.g., OUTPUT) using the input signal (e.g., INPUT) and the EN/SET input connected to a sensing circuit 20. The sensing circuit monitors the EN/SET signal at the EN/SET input and determines if that voltage is constantly high, constantly low, or toggling. Based on this determination, the sensing circuit 20 outputs two types of signals: a periodic signal or clock signal (CLOCK) and an enable signal (ENABLE). The clock signal and the enable signal control operation(s) of an N-bit counter 30. The counter 30 counts rising transitions of the clock signal whenever the sensing circuit 20 asserts the enable signal. The counter 30 is reset when the enable signal is not asserted.
As shown in FIG. 1, the counter 30 receives both the clock and enable signals. The first rising transition of the EN/SET signal raises the enable signal ENABLE and causes the EN/SET signal to be forwarded as the clock signal cycles. The counter 30 responds by increasing its value to one at the first rising edge or high logic level of the clock signal, for example. The subsequent rising transitions cause the counter 30 to increment its value to two, three and so on. The counter 30 is reset to zero when the sensing circuit 20 transitions the enable signal ENABLE to a low value. An N-bit output of the counter 30 controls a ROM 40. The ROM 40 has a total of 2N words, each having M bits. Each M-bit word corresponds to one control state for the circuit. The N-bit output of the counter 30 selects a particular M-bit word within the ROM 40. The selected control state and the enable signal are passed to the core portion 10. The core portion 10 is configured to adjust its operation to match the selected control state.
However, the conventional single wire interface device employs a pulse counting technique in which as many clock cycles as data words in ROM 40 are required. For an example, 256 bits may be required to transmit “256” as a numerical data word, and thus, the efficiency of using the clock is low when the amount of data is large. When a large amount of data is transmitted, such inefficient clock use causes a problem in that transmission speed becomes slow, and power consumption increases depending on the number of times the clock signal switches.